Power Optimization in VLSI Layout: A Survey
نویسندگان
چکیده
This paper presents a survey of layout techniques for designing low power digital CMOS circuits. It describes the many issues facing designers at the physical level of design abstraction and reviews some of the techniques and tools that have been proposed to overcome these difficulties.
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عنوان ژورنال:
- VLSI Signal Processing
دوره 15 شماره
صفحات -
تاریخ انتشار 1997